What do you use to build your next high-performance hardware platform when there isn’t time to build an ASIC or the right ASSP doesn’t exist?

Xilinx’s Virtex®-7 2000T is the world’s highest capacity programmable chip built using the revolutionary 2.5D Stacked Silicon Interconnect (SSI) technology enabling designers to accelerate large complex system deployment. This webcast walks through the key design requirements and techniques to implement designs for ASIC replacement, integrating multi-chip designs and emulation of large ASIC designs.

In this webcast, attendees will learn:

  • Benefits of implementing large complex designs using Virtex-7 2000T FPGA
  • Overview of the 2.5D stacked silicon interconnect technology
  • Review of design requirements—architecture, techniques and system level considerations to build large logic designs

Panch Chandrasekaran, Product Line Manager, Virtex-7 FPGA, Xilinx
Panch Chandrasekaran is the Product Line Manager for Virtex-7 FPGAs at Xilinx. Panch’s responsibilities include managing the Virtex-7 product line life cycle—product strategy, driving cross functional solution teams, development and execution of the product go to market plan. Prior to this, Panch has worked as a high speed signal expert marketing and designing 2.5 Gb/s through 40 Gb/s circuits. Panch has a MSEE in Device Physics from University of Central Florida and an MBA from UC Berkeley Haas School of Business and Columbia University.