Power Issues for Chip and Board Webinar
Power used to be a secondary concern when it comes to chip or system design, but with the rapid rise in importance of mobile devices, increasing chip densities, and a rise in the levels of concurrency, power consumption, power dissipation, heat dissipation, and power integrity and becoming major primary design considerations at all stages in the design flow. Many chip design techniques are making this problem more difficult, such as multiple power domains and clock gating, while high speed interfaces are creating problems with board layouts and 3D packaging techniques are raising many kinds of new challenges. Power management is an important topic for every design company to remain competitive, to increase yields and to deal with the longevity issues required for emerging industries such as automotive.
In this webinar I will be joined by Arvind Shanmugavel of Apache (Ansys) and Randy White of Tektronix. Make sure you don’t miss out on this excitement by registering here.
Brian Bailey – keeping you covered
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