Verifying various vendors’ IP blocks and whole SoCs is tough work. And it’s made tougher by the tedious and detailed work required to set up a comprehensive verification environment from scratch. With such additional challenges as the need to support new interface protocols, limited staff and expertise, and no time or money to change tools or methodologies, it’s no wonder verification can be up to 70% of the SoC’s development cost. In this webinar we will offer an argument for an alternative: a complete, turnkey environment of verification IP, tools, and consistent user interface that will allow you to focus your resources on meeting your coverage targets on schedule, not on holding together your legacy verification methodology.

You will learn:

  • Where inefficiencies, even down to small details like inconsistent user interfaces, cause productivity leakages in test bench setup
  • That eliminating these inefficiencies can improve both your productivity and the final quality of the design you are verifying
  • The specifications of a complete off-the-shelf verification environment, including verification IP and provision for memory structures, which can improve the verification efficiency and quality of your IP blocks and SoC and help you overcome time, resource, and budget constraints.


Susan Peterson, Director of Product Management for Verification IP and Memories, Cadence
Susan Peterson is Director of Product Management for Verification IP and Memories at Cadence. Susan has worn many hats in her 20+ years in EDA including engineering, sales, and marketing. In addition to her responsibilities at Cadence, Susan is an active contributor to the MIPI Alliance.