VCS Productivity Technologies – reducing the growing verification cycle
Learn about VCS’ most recent technology advancements and new features enabling productivity in the following key areas:
- Performance and capacity
- Verification planning
Who should attend
IC design engineers, verification engineers, and managers who want to learn new techniques to improve verification productivity and predictability.
What You Will Learn:
You will learn about the new capabilities available within the most recent verification technology and product release, VCS 11.03. You will learn how to utilize these capabilities effectively to improve overall productivity and predictability including how to increase your verification turnaround time and how to achieve your performance and coverage goals.
Senior Staff Application Engineer (Verification Methodology)
Shekhar Mahatme joined Synopsys 15 years ago and he supports the deployment of state-of-the-art functional verification methodologies and tools. As a verification expert, Shekhar has successfully executed numerous verification projects that included specific technologies, languages and methodologies such as mixed signal verification, mixed HDL simulation, SystemVerilog, VMM and UVM.
Prior to joining Synopsys, Shekhar was a senior member of Silicon Interfaces Inc., a design and verification consulting group. Shekhar holds an MSEE from the University of Iowa and a BSEE from the University of Poona in India.
Director of Product Marketing
Synopsys Functional Verification
Michael Sanie is director of verification product marketing at Synopsys. He has more than 20 years of experience in semiconductor design and design software. Prior to Synopsys, Sanie held executive and senior marketing positions at Calypto, Cadence and Numerical Technologies. Sanie started his career as a design engineer at VLSI Technology and holds four patents in design software. He holds BSCEE and MSEE degrees from Purdue University and an MBA from Santa Clara University.
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