Utilizing Design Compiler 2010 Technologies to Double Synthesis and P&R Productivity
Design Compiler 2010 with its innovative technologies, doubles the productivity of synthesis and place & route. This is a follow up to our previous webinar which was broadcast on April 20, 2010. In this webinar, we will demonstrate how you can deploy and take advantage of the new Design Compiler 2010 technologies. Learn how it enables RTL designers to perform floorplan exploration while still in synthesis. See how you can edit/create your floorplan from with-in synthesis environment to address design issues such as timing violations or routing congestion. Discover how you can produce physical guidance to IC Compiler, place-and-route solution, to tighten timing and area correlation to 5% while speeding-up IC Compiler placement optimization runtime by 1.5X. This webinar will also show how you can speed-up your synthesis runtimes with Design Compiler 2010 by utilizing quad-core compute servers.
Participate in live the Q&A and get your answers in real time from the following members of the Synopsys’ Design Compilers product team.
Who should attend:
Design Engineers, Verification Engineers and Engineering Managers.
Director of Marketing, RTL Synthesis
Priti Vijayvargiya has product marketing responsibilities for RTL Synthesis product line at Synopsys in July 2001. She has 18 years of industry experience gained from working at companies such as Cisco, Compass Design Automation. Trident and Adaptec. Priti received a MS degree in computer science from the University or Indore, India. She has her MBA from Santa Clara University, California.
Sr. Director, Corporate Application Engineer
Sandra Ma is the Sr. Director in RTL Synthesis Corporate Application Engineer Team at Synopsys. Sandra has been with Synopsys for over 15 years and holds a bachelors degree in computer science from Massachusetts Institute of Technology (MIT). Sandra’s team has been a key driver in bringing customer requirements to drive product direction and ensuring easy adoption and customer success with the new technologies such as topographical technology.
Staff Corporate Application Engineer
Alak Ghosh is a Staff Corporate Applications Engineer for Design Compiler at Synopsys. Alak has been working with the RTL Synthesis product line at Synopsys for the past 9 years. Alak is also responsible for the Design Compiler Reference Methodology which serves as a reference for running the Synopsys RTL Synthesis flow. Alak received a bachelor’s degree in electrical engineering from the University of Waterloo, Canada. He also holds a masters degree in neurological sciences and a bachelors degree in physiology from McGill University, Canada.
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