SoC designs today include design-for-test (DFT) techniques to enable automated, high-quality manufacturing tests. Besides minimizing the number of defective parts shipped, this same infrastructure also enables automated, precise isolation of silicon defects. By applying proven diagnostics techniques on a volume of failing devices, systematic yield issues can be quickly identified, thus enabling faster yield ramp. This webinar will demonstrate how TetraMAX ATPG and Yield Explorer leverage existing DFT infrastructure and design information to provide a fully automated diagnostics solution for rapid failure analysis and yield ramp. An interactive Q&A session will take place following the technical presentation.

Cy Hay
Technical Marketing Manager

Cy Hay is responsible for marketing the TetraMAX ATPG product line at Synopsys. Previously he was a test consultant and applications engineer for Sunrise Test Systems, and a microprocessor designer at Hewlett-Packard. He has over 25 years of experience in semiconductor design, verification and test methodologies, and holds 3 patents in the field of test automation. Cy received his BSEE from the University of Cincinnati.

Girish Patankar
Principal Engineer

Girish Patankar is a Principal Engineer with the TetraMAX team at Synopsys, Inc. Girish has held various technical and management positions for the DFT Compiler and TetraMAX teams in his 15 years at Synopsys. Prior to joining Synopsys, Girish worked for the Design Automation Division at Texas Instruments. Girish has a B.Tech from Indian Institute of Technology, Kanpur and an M.S. from the University of Iowa, Iowa City.

John Kirkland
Corporate Applications Engineering Manager

John Kirkland has a BSEE from the University of Texas at Austin. He has worked for KLA-Tencor, HPL, and Synopsys in their yield management software teams over the past 16 years. John currently manages the Corporate Applications Engineering team for the Yield Explorer product.