Using Foundation IP in Low-Power 40nm IoT Designs
With foundries close to qualifying eFlash at 40nm, the 40nm node will soon become the preferred node for chips targeting Internet of Things (IoT) applications. Processes such as TSMC’s 40ULP technology offer expanded threshold voltages (VT), long channel lengths and innovative circuits like multi-bit flip flops to reduce power.
This webinar will provide details on how foundation IP—logic libraries and embedded memories—can help designers of IoT applications take advantage of the power benefits available in 40nm process technologies. It will describe:
- Why the 40nm process is gaining traction in IoT applications
- How memory compliers can leverage assist circuitry to support the lowest operating voltages
- How ultra-low leakage libraries can be used to build always-on logic blocks, reducing leakage by up to 100X
- How always-on logic blocks can connect directly to a wide variety of energy sources while bypassing voltage regulators
Who Should Attend:
IoT system architects, SoC designers
Ken Brock, Product Marketing Manager, Logic Libraries, Synopsys
Ken Brock is Product Marketing Manager for Logic Libraries at Synopsys and brings 25 years of experience in the field. Prior to Synopsys, Ken held marketing positions at Virage Logic, Simucad, Virtual Silicon, Compass Design Systems and Mentor Graphics. Ken holds a Bachelor’s Degree in Electrical Engineering and an MBA from Fairleigh Dickinson University.
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