Using ESP-CV for Faster Redundancy Verification in Memory Designs
ESP-CV performs functional equivalence checks between a Verilog design and its transistor level implementation. The designs may be described as Verilog behavioral models, RTL, or gates, and a SPICE netlist. The new redundancy verification features in ESP-CV provide the ability to quickly and efficiently verify memory designs implemented with row and column redundancy.
CAE, Implementation Group, Synopsys, Inc.
Dave is a CAE for ESP-CV, with more than 30 years of experience in custom digital design and EDA. He holds a Bachelor’s degree in Electrical Engineering and Computer Science from Princeton University. He did CPU design for RCA, worked in SOS, bi-polar and GaAs technologies, managed ASIC design groups at ZyMOS, applied formal methods to memories at Chrysalis and enjoys symbolic simulation at Synopsys.
R&D Manager, Implementation Group, Synopsys, Inc.
Clay is an R&D manager for ESP-CV, with 13 years of experience in custom digital design and EDA. He holds a PhD in Electrical and Computer Engineering from Carnegie Mellon University, where his research focused on the formal verification of transistor-level designs. He also holds Bachelor’s and Master’s degrees in Electrical Engineering from Georgia Tech. Prior to joining Synopsys, he worked in HP’s Microprocessor Technology Lab, responsible for designing various full-custom blocks on PA-RISC and Itanium processor projects, performing post-silicon power characterization, and analyzing chip-level timing.
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