USB 3.0 Superspeed PHY Testing Challenges: Verify your 5Gbps design to the specification
What do you need to know about physical layer compliance measurements for USB 3.0? At 5 Gbps your jitter margins for Superspeed USB are a tiny fraction of what you had for USB 2.0. On top of that you will have to consider de-emphasis levels, spread spectrum clocking, receiver jitter tolerance testing and new cables and connectors taking margin from your design.
This presentation covers the USB 3.0 testing challenges you face for motherboard, device and channel testing as you move to 5Gbps performance levels. You will learn where you can recover the margin in your design through advanced testing techniques such as fixture de-embedding. You'll also learn about the effect of instrument noise in jitter analysis and how to ensure you understand benefits of selecting instruments with the lowest noise floor. Lastly you will learn about the USB 3.0 specification requirements for transmitter and receiver testing and how to test to those requirements.
Duration: One hour
Who should view this webcast:
USB Design Engineers, Signal Integrity Engineers, Quality Engineers, Validation Engineers, Test Engineers, Architects, Project Managers, Program Managers, Application Managers, and Application Engineers
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Jim Choate, Product Manager – Measurement Technologies, Oscilloscopes Division, Agilent Technologies
Jim Choate received a Bachelors degree in Electrical Engineering from the University of Idaho in 1997 and started with Intel working on motherboard design and validation. Building on his platform expertise he joined the Intel C&I team in 1999 working on specifications and compliance programs for USB 2.0, SATA, PCI Express, WUSB and WiMedia UWB PHY testing. Jim joined Agilent Technologies, Inc. in 2007 as an Applications Specialist and Product Manager for the Oscilloscopes Division where he will continue to apply his expertise in measurement theory to USB 2.0, Wireless USB and PCI Express 2.0 compliance and measurement theory.
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