Overview:
Achieving your aggressive design goals combines numerous hurdles. Not only are you working to achieve higher performance targets, leverage more advanced FPGA architectures, and adhere to tighter power budgets, but development schedules also continue to shrink. The cliche of “doing more with less” is a driving theme in today’s FPGA design flows.

Xilinx ISE Design Suite 12 is the production-optimized tool suite for Virtex-6 and Spartan-6 FPGAs that delivers innovation in three critical areas of concern for FPGA design: power reduction, productivity and performance. This webcast will present an overview of key achievements and advances in each of these three categories. This webcast will also describe the next generation Partial Reconfiguration design flow to help designers reduce the size, cost and power consumption of a design.

Attendees will learn:

  • How new automated, intelligent clock-gating technology in the ISE Design Suite 12 can help reduce dynamic power by as much as 30%
  • How to accelerate the overall design process using the Design Preservation flow to partition and lock down placement and routing of timing-critical portions of a design
  • How to leverage the fully optimized place-and-route and synthesis algorithms in the ISE Design Suite 12 to improve Quality of Results (QoR) and significantly decrease synthesis and implementation times.

Presenter:
Hitesh Patel, Director of Software Product Marketing, Xilinx
Hitesh Patel joined Xilinx in 1997. As director of Software Product Marketing at Xilinx, Patel is responsible for leading a team of technical marketing engineers who drive tool requirements and strategies for Xilinx software.

Patel brings more than 15 years of design, management and marketing experience to Xilinx. Prior to Xilinx, Patel spent several years at Actel Corporation in a variety of technical marketing and applications engineering positions.

Patel holds a bachelor of science in Electrical Engineering degree from City University, UK and a master of science in Electrical Engineering degree from the University of Arizona.