Understanding the Risk Factors Associated with Repetitive Avalanche in Power MOSFETs
As Power MOSFET vendors increase the switching speed of their MOSFETs, voltage transients related to the high di/dt, and the parasitic inductances of PCB layouts become harder for the designer to control. In this live webinar, we will examine the risk factors associated with repetitive Avalanche. Topics covered:
- Describe potential failure mechanisms within the mosfet structure due to avalanche
- Show how these are failure mechanisms are minimized with NXP Trench MOSFETs
- Discuss how to avoid common applications pitfalls which cause avalanche
- Demonstrate how to estimate the repetitive avalanche capabilities of NXP Mosfets
Please join us to learn more about the risk factors that need to be considered for stable long-term operation.
Edgar Ayerbe works as a Product Marketing Engineer with NXP, Americas, and is based in Cary, NC. Edgar has responsibility for the driving the technical marketing solution, proving marketing support and expertise to NXP's Multi-Market Semiconductor (MMS) business unit. Prior to NXP, Edgar spent over ten years as an engineering manager with Qimonda. He also worked as an application engineer with Teradyne in the Semiconductor Industry. Edgar has completed a Bachelor of Science degree in Computer Engineering from Rensselaer Polytechnic Institute.
Phil Ellis is a Concept Engineer for low voltage power Mosfets with NXP, based in Manchester, United Kingdom. Phil's role is to understand market technical requirements and translate these into new product requirements and to provide technical support for customers. Phil has 20 years of experience in the design of power electronic circuits in industrial, consumer and aerospace fields. Phil has a Bachelor of Engineering degree from the University of Newcastle upon Tyne.
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