Understanding PCI Express(R) 3.0 and How to Implement the New Features
The next generation of the PCI Express(R) protocol, PCI Express 3.0, incorporates significant changes that go beyond the increase in link speed from 5 GT/s to 8 GT/s. For example, the Physical Layer encoding scheme has been completely changed and new training sequences have been added to achieve optimal equalization settings at 8 GT/s. In this webinar:
- Hear about the key specification changes for the PCI Express 3.0 protocol, equalization procedure, PIPE interface and electrical interface
- Learn about the trade-offs and practical implementation issues that will be discussed through examples and lessons learned from the development of Synopsys DesignWare IP for PCI Express 3.0
- Get a brief overview of the DesignWare® IP for PCI Express 3.0 solution
Who should attend:
Designers that have already developed a high-performance SoC with PCI Express 1.x or 2.0 and are looking to understand the changes to the protocol and its effect on the implementation of their next-generation SoC using PCI Express 3.0.
50 minutes, 10 minutes Q&A
Frank Kavanagh, Senior Engineering Manager, DesignWare Digital Controllers for PCI Express, Synopsys
Frank Kavanagh is the senior engineering manager for the DesignWare Digital Controllers for PCI Express. He joined Synopsys in May 2001 as an R&D manager for the DesignWare Library AMBA product line and has worked on both AXI and AHB system-on-chip infrastructure. From there Frank moved to manage the DesignWare DDR protocol and memory controller digital cores and was the project lead for DDR testchips. Before joining Synopsys, Frank worked in Partus developing SoC reference design for the Bluetooth market. Frank holds a masters degree in Microelectronics majoring in microwave IC design from University College Cork.
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