DDR4 speeds require key AC timing parameters
such a tDIVW, tDS, tDH to be defined and measured in a new way. The traditional
assumptions that as long as tDS/tDH were met there would be zero errors have
never actually been true and have forced costly and time-consuming over-design
of controllers, DRAMS and systems. DDR4 addresses this issue head on by
accounting for real-world random and deterministic jitter at a Bit Error Rate
(BER) that assures system stability while eliminating the need for expensive
over-design. This session will explain the new AC parameters in depth and show
you how to measure them, allowing accurate device characterization and system
validation without costly timing surprises at system integration.

Who Should View this Webcast
Memory Chip Designers,
Memory Chip Integrators

Keller, Program Lead for Applications and Standards, Digital Test Division,
Agilent Technologies

Perry Keller manages Agilent’s Memory
Application Program. He has over 25 years of experience at Agilent Technologies
in the areas of software and system engineering, high speed hardware and ASIC
design and validation, software engineering, product marketing, and project
management. Perry graduated in 1980 from Rice University with a Masters Degree
in Electrical Engineering.