With over 240 different fault types, accurately testing memories is extremely complex. Exhaustively testing memories would be test time prohibitive. Designers must implement an efficient and accurate approach to ensure high quality while maintaining optimal test cost.

Moreover, densely packed memory arrays structures are highly susceptible to defects and are a dominant factor in determining chip yield. Accurate memory diagnosis and repair are key requirements for maximizing yield.

In this webinar, TSMC, a leading semiconductor manufacturer, describes the major memory test challenges they face when manufacturing billions of chips across multiple market segments each year. They will discuss the factors influencing their selection of DesignWare® STAR Memory System to characterize their SRAMs at advanced nodes. They will present the benefits of unique features within STAR Memory System, such as the Multi-Memory Bus (MMB) Processor, which enables area and performance-optimized test and repair of high performance cores. They will also highlight the comprehensive memory modeling and diagnostic features that enable efficient silicon bring-up and characterization. They will share the test chip architecture which includes an illustration of how they leveraged the MMB processor to seamlessly interface to the ARM® Cortex® shared test bus architecture. SMS is fully supported by TSMC SRAM IP kits.

After the webinar, attendees will understand:

  • Why TSMC selected STAR Memory System
  • How TSMC uses STAR Memory System’s memory test and diagnostic features to characterize their memories
  • STAR Memory System’s comprehensive memory modeling language and validation flow at advanced nodes
  • How the Multi-Memory Bus Processor provides a seamless test and repair interface to high performance cores including the ARM Cortex-A15 shared test bus architecture.

Who Should Attend:
Who should attend:
SoC Designers, Architects, DFT engineers, Test engineers, Product Engineers and foundry engineers who are, or will be, designing, testing or characterizing SoCs with embedded memories.


Saman Adham, Ph.D.

Dr. Saman Adham received a BS and MS in Electrical Engineering from the University of Baghdad, Iraq, in 1977 and 1979 respectively and his PhD from Queens University, Canada in 1991. Dr. Adham has over 25 years of industrial experience with a proven track record in the area of design for test (DFT) and built-in self-test.

Prasad Saggurti

Prasad Saggurti is the Product Marketing Manager for Embedded Memory IP at Synopsys. Prior to Synopsys, Prasad held senior engineering and marketing roles at MoSys, ARM, National Semiconductor and Sun Microsystems. Prasad has an MSEE from the University of Wisconsin-Madison and an MBA from the University of California-Berkeley.