Overview:
The evolution of multi-core CPUs and ICs has led to increased complexity and new challenges for routing completion on these circuits. Current ‘industry standard’ routers provide users with powerful routing engines that enable large digital blocks to be routed successfully at advanced process nodes.
However, industry standard routers were not designed to address the challenges of routing between digital cores with many metal layers. Different routing topologies are required with a structured approach to routing tens or hundreds of thousands of wires all with matched topologies (bus and template styles), matched lengths and matched layers at advanced process nodes of 45nm and below.
In this webinar you will learn about this industry trend from eSilicon and how you can overcome these challenges using custom design tools provided by Pulsic. These tools enable engineers to achieve fast and efficient DRC/LVS correct completion of top level routing and floorplanning tasks.
In this webinar, attendees will learn:

  • why custom design tools including shape based routers, provide more optimal use of area and a more flexible floorplanning and routing solution for multi-core designs
  • how a custom design tool can provide faster completion of top level, DRC correct routing in multi-core designs
  • how to easily set up top level routes as structured routing topologies, even on highly congested circuits to improve yield
  • how to set up matched routes to improve signal integrity
  • Presenters:

    Prasad Subramaniam, Ph.D. Vice President, Design Technology, eSilicon
    Prasad Subramaniam is responsible for developing eSilicon’s technology platforms for IC design. From 1982 to 1998, he was with Bell Laboratories, where he held a variety of technical and management positions culminating as the Head of Analog and RF CAD. In that role, he was also responsible for modeling and characterizing the semiconductor technologies used by IC designers at Lucent. Dr. Subramaniam joined Cadence Design Systems as VP of R&D in 1998. He has a wide range of experience in ASIC, custom and mixed signal design. He holds a Ph.D. degree in Electrical Engineering from the State University of New York at Stony Brook.  

    Mark Waller, Co-Founder and Vice President of Research and Development, Pulsic

    Mark graduated from Loughborough University in England with a degree in Electronic Engineering and Physics. He then joined Zuken in the UK as a software developer working in the routing development team on PCB routing technology. And later working on IC routing technology for Zuken. In early 2000 Mark and his fellow co-founders started Pulsic with Mark heading up the Research and Development teams.