Overview:
Serial I/O provides high bandwidth for connecting chips, boards, and boxes while consuming less power and PCB real estate than traditional parallel interface technologies. The latest generation of Xilinx FPGAs offers a portfolio of transceivers that deliver power-efficient, cost-efficient support for mainstream and emerging serial interface standards at 3Gbps, 6Gbps, 10Gbps, and beyond.

Learn how to select the proper transceiver for building robust serial interfaces in your next project. In this webcast we review the capabilities of the 3.125Gpbs GTP transceivers in Spartan-6 LXT FPGAs, the 6.5Gpbs GTX transceivers in Virtex-6 LXT and SXT FPGAs, and the 11.2Gpbs GTH transceivers in Virtex-6 HXT FPGAs. Using application examples from the wired telecommunications, wireless infrastructure, and audio/video broadcast industries we explore the issues that designers must consider when choosing a serial I/O-enabled FPGA. Finally, we discuss how to configure these multi-rate transceivers for reliable implementation of serial links based on key interface standards.

Webcast Attendees Will Learn:

  • The key features and capabilities of multi-gigabit transceivers in Virtex-6 and Spartan-6 FPGAs
  • How to choose the appropriate FPGA/transceiver combination for their next design
  • How to configure GTP, GTX, and GTH transceivers for reliable implementation of industry standard and customer serial interfaces at 3Gbps, 6Gbps, 10Gbps, and beyond
  • Who Should Attend:

  • Hardware system designers
  • System architects
  • Project managers
  • Presenter:

    Anthony Torza is a Technical Marketing Engineer for Xilinx specializing in SERDES products. He has been with Xilinx for 4 years. Previously he was a System Architect and Hardware design engineer for various telecom equipment companies including CIENA and Tellabs. He holds an MSEE from Stanford.