The Art of Integration - Performance & Layout Optimization Techniques for Advanced Analog/Mixed-Signal SoC Designs
The integration of full custom analog circuitry into a silicon chip, to provide cost-effective products, requires a full understanding of the process architecture and uses completely different methods compared with those used for digital designs. This webinar will briefly cover the digital design arena before entering into in-depth discussion of analog layout techniques. It will explore the integration of X-FAB-supported primitive devices into complex integrated chips in detail, including diffusions, wells and associated layers that can be merged. The session will also cover derivation of “well” combinations from the design layers, and give guidelines for high-voltage interconnects across these well regions to avoid parasitic leakage paths.
These design techniques will be showcased in X-FAB’s 0.35m high-voltage process, but they are applicable to a broad range of analog/mixed-signal process technologies.
Jim Tomkins, Design Consultant, X-FAB Group
Jim Tomkins is a member of the X-FAB Hotline engineering team providing technical support and solutions to X-FAB customers during the design phases of their product development. Prior to joining X-FAB, he has worked at the Plessey Research establishment, Caswell, and Plessey Semiconductors manufacturing unit in Plymouth which has been owned by GEC, Mitel, Zarlink Semiconductors and X-FAB Semiconductors over a 22 year period. He managed the ASIC development team in Plymouth responsible for the creation and layout optimisation of gate array and standard cell architectures. Jim has a total of more than 42 years design experience in the industry specialising in bipolar and CMOS integration.
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