Are you keeping pace with the demands of designing the next product breakthrough? Increasing requirements in architecting and validating performance, memory and power consumption might require you to look beyond your traditional verification methods. As a designer, you will face many challenges during the SoC design cycle, such as the architecture might change, bus speeds can vary, peripherals may be added or removed; the software becomes more complex. How do you know that your selection of memory will keep up with all of these changes?

This Synopsys technical webinar will discuss how feature-rich, native SystemVerilog memory VIP can rapidly verify the memory interfaces on your most complex designs, focusing on 10 key areas where productivity is improved. It will also show how the next generation memory VIP can verify the JEDEC protocol or can be configured to model specific memory devices. Additionally, many features to ensure efficiency and usability will be covered, including coverage, protocol aware debug, protocol and timing checks, memory array viewing and backdoor access.

Attendees Will Learn:

  • Dynamic part selection; no need for re-compilation when selecting new part
  • Intelligent, built-in JEDEC compliant Protocol and timing checks
  • Pre-defined CoverGroups for Memory State transition, training and power down modes, and more
  • Direct testbench access to the Memory Core for peek, poke, and set/get/clear any memory location attributes
  • Error injections into transactions
  • Synchronized debug between transactions and signals


Nasib Naser, PhD
Senior Staff Corporate Applications Engineer, Synopsys

Nasib is a Senior Staff Corporate Applications Engineer in the Verification Group for Synopsys, lnc. He has extensive experience in System-on-Chip (SoC) Design and Verification, Embedded Systems Design, and Computer Architecture. Nasib spent more than 15 years in EDA where he led many customers’ design and verification projects using SystemC and later SystemVerilog. Currently, Nasib leads and manages customer’s Memory VIP engagements in North America. Overall, Nasib has over 30 years of experience as a technical applications engineer. In addition to Synopsys, he has previously worked at NASA/Ames, Varian, and CoWare.

Neill Mullinger
Product Marketing Manager for Verification IP, Synopsys

Neill Mullinger is a product marketing manager at Synopsys for verification IP. Neill joined Synopsys in 2000 and has been focused on verification IP and protocol verification since 2002. He brings more than 25 years of experience in the hardware and EDA industries as an applications engineer and product manager.