To deploy complex electronic systems for in-vehicle safety-critical functions, automakers work with their suppliers to ensure that the methods and tools used from design to field operation are compliant with safety standards including ISO 26262.

This webinar will discuss the implications of automotive test, reliability and functional safety requirements on all aspects of the SoC lifecycle: design, silicon bring up, volume production, and in-the-field power-on self-test (POST). We will also discuss the automotive safety-critical designs that may need periodic in-system self-test and error correction. We will show solutions that help create functionally safe ICs and SoCs, including special embedded test and repair capabilities leveraged from manufacturing to mission mode; advanced error correcting codes (ECC) to detect and correct multi-bit upsets during in-system operation; process and clock monitoring, and fault injection for comprehensive silicon debug.

Attend this webinar to learn about:

  • Design, test, reliability and safety requirements that are specific to automotive ICs
  • How automotive test solutions across heterogeneous cores (memories, logic blocks, AMS and interface IP) support such requirements, while minimizing cost due to concurrent test, test power reduction, effective DFT closure, isolated debug and diagnosis, pattern porting and reuse, self-calibration, and uniform test access
  • How incorporating Self-Test & Repair (STAR) infrastructure with high-efficiency test and repair capabilities can help minimize the impact on power, performance and area, while addressing the need for very low Defective Parts Per Million (DPPM)
  • Benefits of selecting an ISO 26262 certified embedded test & repair IP to accelerate time to market for SoCs, while meeting functional safety requirements

Who should attend:
SoC designers and system/chip architects who are interested in design, test, reliability and safety requirements for automotive ICs.


Yervant ZorianYervant Zorian, Fellow & Chief Architect, Synopsys

Dr. Zorian is a Chief Architect and Fellow at Synopsys. Formerly, he was a Distinguished Member of Technical Staff AT&T Bell Laboratories, Vice President and Chief Scientist of Virage Logic, and Chief Technologist at LogicVision. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.

Faisal M. GoriawallFaisal M. Goriawall, Product Marketing Manager, Synopsys

Faisal M. Goriawalla is the Product Marketing Manager for Synopsys’ DesignWare NVM IP and Embedded Test and Repair. He has over 13 years of design engineering and marketing experience in embedded physical IP. Mr. Goriawalla started his career developing embedded memory compilers and previous to Synopsys held various technical and marketing positions for memories, standard cells and IO libraries at ARM and Lucent Technologies. Mr. Goriawalla holds a Master of Science Degree in Electrical and Computer Engineering from North Carolina State Univ