SuperSpeed Your SoC with USB 3.0
Consumers are demanding higher bandwidth for faster data transfer of video, pictures and music for the next generation of consumer electronic applications such as storage devices, camcorders, digital media players and smartphones. To address this demand, the new USB 3.0 (aka SuperSpeed USB) standard operates at 5Gbps and delivers more than 10x the bandwidth of USB 2.0, enabling faster "sync-and-go" functionality between PCs and portable electronic devices.
In this seminar you will learn:
- What is driving the need for USB 3.0
- The key differences between USB 2.0 and USB 3.0 at the protocol and electrical levels
- What to look for when evaluating a USB 3.0 IP solution
Who Should Attend:
ASIC Design Engineers, Designers of complex, high-performance systems, System architects and Engineering or Technical Managers
Max the Magnificent
Clive "Max" Maxfield has now spent over a quarter of a century in the electronic, computing, and EDA arenas. In 1980, after obtaining his BSc in Control Engineering (an interesting mixture of math, electronics, mechanics, and hydraulics and fluids), Max joined a design team at International Computers Limited (ICL) creating CPUs for mainframe computers. In addition to designing ASICs and circuit boards, Max has written numerous test programs for functional and in-circuit testers. In the area of digital logic simulation, Max has created models of everything from ASIC cell libraries to microprocessors. Due to his digital expertise, Max was once appointed analog marketing manager at a large EDA company (the world is a funny old place sometimes).
In the early 1990s, Max thought it would be fun to see a book he'd written on the shelves in his local book store, so he penned his first tome Bebop to the Boolean Boogie (An Unconventional Guide to Electronics). Since that time, Max has authored and co-authored a number of books, including EDA: Where Electronics Begins, The Design Warrior's Guide to FPGAs, and How Computers Do Math (Featuring the Virtual DIY Calculator).
Dr. Robert Lefferts, PhD, R&D Director, PHY IP Group, Synopsys
Dr. Lefferts has more than 25 years of experience in the semiconductor industry. He received his PhD in Electrical Engineering from Stanford University in 1981. He is currently the director of the Hillsboro PHY development group which is responsible for Synopsys' high speed SERDES IP serving PCIe, SATA, XAUI and USB 3.0 applications. Prior to Synopsys, he was the Director of Engineering at Accelerant Networks, a fabless semiconductor company in the high speed transceiver market that was acquired by Synopsys in 2004. His interests include high speed SERDES and analog design, technology development, design support, and semiconductor device modeling and characterization. Prior to Accelerant Networks, he worked at Lattice Semiconductor, where he was responsible for all aspects of design integrity and cell reliability for advanced CMOS nonvolatile programmable logic devices.
Subramaniam Aravindhan, R&D Manager, IP Group, Synopsys
Subramaniam Aravindhan (Arvind) has been with Synopsys for over 10 years. He is currently an R&D Manager in the IP group, where he is responsible for the development of USB 3.0 digital controllers and was previously involved with USB 2.0 and Wireless USB IP. Before joining Synopsys, Arvind was a hardware engineer at Logic Modeling until its acquisition by Synopsys. He received a Masters degree in Electrical Engineering from Anna Uni
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