The PCI Express 5.0 specification doubles the data rate from 16GT/s to 32GT/s and provides up to 128GB/s in bandwidth, offering a fast interconnect technology for high-end computing and emerging artificial intelligence applications. However, implementing this higher level of performance requires designers to consider and overcome several key challenges including managing datapath width, timing closure, signal integrity, and complex packaging issues. In addition, a close collaboration between system designers, SoC designers, and layout designers becomes important. Attend this webinar to find out how to accelerate your move to 32GT/s PCIe designs while managing the latency, throughput, power, and area requirements.

Attendees will learn:

  • Ways to overcome key PCIe design challenges at 32GT/s: Design, Integration, packaging, performance, timing closure
  • How to successfully implement the latest PCIe 5.0 technology


Gary Ruggles Sr., Product Marketing Manager, Synopsys

Gary Ruggles is the Sr. Product Marketing Manager for PCIe, CCIX, and SATA Controllers. Gary has over 25 years of experience in the semiconductor industry, and has spent the last 17 years in sales, marketing, and business development roles for multiple semiconductor IP companies, including PLDA, Kool Chip (now Invecas), Snowbush IP, ARM/Artisan and Cadence (Tality), focusing on PHYs and PCIe controller IP. Gary holds a PhD in Electrical Engineering from Penn State University.