Successful Formality Equivalency Checking for Low-power Designs – Tips from the Experts
In this webinar, you will learn how to optimize comprehensive, low power verification with UPF using Formality. Our expert will share tips and tricks that simplify the process of low power verification, including debug and best practices. Following the technical presentation, an interactive Q&A session will take place.
Bob Hatt, Corporate Applications Engineer, Synopsys
Bob Hatt is a Staff Corporate Applications Engineer at Synopsys working on Formality. He has over 25 years experience as a design engineer, technical instructor, and applications engineer, spanning the areas of design, simulation, modeling, synthesis and formal verification. He has held technical positions at Hughes Aircraft, Mentor Graphics, Summit Design and now Synopsys. For the last 3 years has been a key contributor to making sure Formality works correctly in the Synopsys Low Power Flow. Bob has a MSEE from Portland State University and a BSEE from the University of Nevada at Reno.
Please disable any pop-up blockers for proper viewing of this webinar.