Standard Cell Benchmarking: Avoiding 5 Common Pitfalls
Proper evaluation of standard cell libraries should lead you to select standard cells that will optimize power, performance and area for your design. Using ARM® Artisan® 28nm libraries as an example, this webinar will discuss general evaluation practices and highlight potential pitfalls which could lead to erroneous results. Topics will include an overview of an optimized power network, alignment to the library architecture, “don’t use” cell lists, edge rates and wire lengths. In addition, the webinar will cover evaluations from synthesis to place and route.
What you will learn by attending the webinar:
- General best practices for evaluating standard cell libraries
- Potential pitfalls that result in suboptimal results during a library evaluation
- Power networks can impact evaluation results
Who should attend:
Any designer or manager interested in learning about how to evaluate standard cell libraries or how to get the best from ARM Standard Cell Libraries.
Target length: 50 minutes with QA
Leah Schuth, Manager of Technical Marketing, Physical IP Division, ARM
Leah is Manager of Technical Marketing group in the Physical IP Division (PIPD) at ARM. One focal point of Leah’s work is enabling successful customer evaluations and adoption of PIPD products. In this role, Leah works with customers, during standard cell library, memory compiler and interface IP evaluations to ensure that the results correctly represent the merits of the IP and how to get the best PPA (power, performance and area) out of the EDA tools and the libraries.
Leah began her career and in standard cell design and development before moving to applications engineering. Leah holds a B.S. in EECS from the University of California, Berkeley.
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