The speed of DDR (Double Data Rate) memory technology has increased rapidly in the last few years. The latest DDR3 technology is operating over 1.6GT/s and at the same time, the signal amplitude has decreased to reduce power consumption. With faster and smaller signals, the designs have fewer margins for error, thus having good signal integrity is important to guarantee reliable system operation. On top of that, a huge DDR validation challenge lies in the signal accessibility of the signals at the BGA package. Without good probing points, the measurement results could be compromised, not reflecting the real performance of your system.

In this webcast, Agilent and Advanced Validation Lab (AVL) will provide some insights into solving the signal integrity and probing challenges for DDR technology, which cover LPDDR, DDR2 and DDR3 memory technologies.

Duration: One hour

Who should view this Webcast:
DDR Design Engineers, Signal Integrity Engineers, Quality Engineers, Validation Engineers, Test Engineers, Architect, Project Manager, Program Manager, Application Manager, Application Engineer

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Min-Jie Chong, Product Manager, Design Validation Division, Agilent Technologies

Min-Jie Chong is the product manager for the Agilent memory test solution for the oscilloscope business segment. He has been with Agilent for 6 years and in addition to his current role has worked in product manufacturing and as a sales support consultant for oscilloscopes.

Larry K. Ho, Director of Technical Labs, Advanced Validation labs (AVL)

Larry K. Ho is the Director of Technical Labs responsible for Advanced Validation labs (AVL) test development & operation, focusing on memory technology validation & OEM qualification testing. He has been working at Kingston & AVL for the last 11 years. Prior to this, he has held Product/Test & Component Engineering jobs at Intel, SGI & others.