Simplified Physical Layer Receiver Test of Re-timed Architectures Such as USB 3.0, SATA, SAS, PCIe 2
Many of today’s digital interface standards use 8B/10B coding and a concept of inserting or removing filler symbols ( Aligns or Skip symbols) to compensate for different clock speeds within the system. With increasing data rates comprehensive physical layer testing gains importance, while this behavior causes a challenge for traditional receiver test instruments. To address this need, Agilent provides a novel concept for error counting with its latest generation Bit Error Ratio Testers (BERT). With integrated 10B/8B decode the BERT becomes agnostic to changes in data coding which are caused by flipping running disparity. In addition, the 10B symbol awareness of the error detector enables the BERT to separate between the expected data and filler symbols. Thus the BERT now operates seamlessly on a re-timed data stream.
The Webcast covers the basics of 8B/10B coding and data re-timing as these concepts are deployed in most common standards. It explains how such receivers are tested with Agilent’s latest J-BERT N4903B. Examples from SATA and USB 3.0 illustrate the benefits of the new approach.
Who should view this webcast:
R&;D engineers who need to characterize the physical layer performance of gigabit serial bus interfaces, such as SATA, SAS, USB3, PCIe™, MIPI
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Dr. Michael Herz
Michael Herz is a digital applications specialist. He is responsible for developing and marketing digital receiver physical-layer test applications such as DisplayPort, MIPI, USB 3.0 and SATA. Herz is an active member in SATA-IO and VESA’s DisplayPort group. Herz received his doctorate from University of Kaiserslautern in Germany, where he worked on reconfigurable computing architectures. He also holds a degree in computer science, with an emphasis on digital design.
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