Full-chip sign-off validation is a critical
challenge for system-on-chip (SoC) design teams. With design sizes often
exceeding 50 million gates, and numerous operating modes and corners to
validate, the number of engineering change order (ECO) cycles has increased
exponentially. This has had an adverse affect on design schedules and time to

Magma’s Silicon One SoC Sign-off technology, including QCP™ for parasitic
extraction, Tekton™ for delay calculation and static timing analysis, and
Quartz™ DRC/LVS, provides a fast, accurate, high capacity solution that speeds
SoC timing closure and validation.

View this webinar now to learn how Magma’s Silicon One SoC sign-off
technologies enhance the overall flow and integrate into a complete sign-off
solution. Here are just some of the advantages that will be covered in the

  • Multi-threaded performance and scalability that consistently out-performs
    traditional tools.
  • Unique multi-mode, multi-corner analysis and extraction capabilities that
    significantly reduce hardware resources through single server, concurrent
  • Integration with the place-and-route environment that eliminates
    miscorrelation between implementation and sign-off timing environments and
    enhances LVS/DRC closure.

Molina, Senior Director, Digital Sign-off Business Unit, Magma Design
Automation, Inc.

Ruben joined Magma in July of 2010 and is currently
responsible for product marketing and business development of Magma’s digital
sign-off products with a special focus on static timing analysis tools.

Ruben has over 20 years experience in electronic design and design
automation. Prior to joining Magma, he held management positions in design
methodology, applications, and technical marketing for LSI Logic and Extreme DA.
He also spent several years as an IC designer for Hughes Aircraft, Radar Systems
Group. Ruben holds a BS in Engineering and MSEE from California State
University, Los Angeles. He is the co-author of seven U.S. patents.