Overview:
PCI Express is everywhere! Servers, storage,
communication and consumer devices are all leveraging this popular technology.
New standards on top of PCIe are arising to address and optimize new
application-driven interfaces (SR-IOV, MR-IOV, Thunderbolt and NVM Express).

Each introduction of a new protocol on top of the already-complex PCIe
design creates new verification challenges that require deep understanding of
the protocols and extensive time and resources to test compliance to the
specifications and optimize performance consumption.

This webinar will
present the technical challenges of advanced PCIe-based design verification, and
the latest methodologies and tools to address them.
Real world case studies,
describing how PCIe and NVMe-based designs can be tested that minimize time and
effort will be presented and analyzed.

This webinar will teach
you:

  • What are the verification pitfalls of PCIe and NVMe protocols
  • What are the best practices for verification of layered protocols like PCIe
    and NVMe
  • How to apply metric driven verification techniques to speed up the
    verification process of PCIe device
  • How to identify performance issues during the verification process
  • How to maximize reuse of verification components when dealing with new
    generations of specification

Estimated length: 40
minutes, 10 minutes Q&A

Who should attend:
This
webinar is targeted at system architects, designers, verification engineers and
project managers

Presenters:
Guoqing
Zhang, Fellow and Verification IP (VIP) CTO at Cadence

Guoqing Zhang
is Fellow and Verification IP (VIP) CTO at Cadence. He has been in the EDA
industry for over 20 years. He holds a BSCS from SJTU in China and MSEE from
Univ. of Arizona.

Moshik
Rubin, Senior Product Line Manager for Verification IP (VIP),
Cadence

Moshik Rubin is Senior Product Line Manager for Verification
IP (VIP) at Cadence. He has been in the EDA industry for over ten years. He
served as Verification IP Engineering manager at Verisity and now manages
several protocols within Cadence’s VIP portfolio including PCIe and MIPI
verification IPs. Mr. Rubin holds a BS in Computer Engineering from the Technion
– Israel Institute of Technology as well as an MBA from Tel-Aviv University’s
Recanati Graduate School of Business.