Data converters are at the center of every
analog interface to systems-on-chips (SoCs). As SoCs move into 28-nm and smaller
advanced process nodes, the challenges of integrating analog interfaces change
due to the process characteristics, reduced supply voltages, and analog blocks’
area requirements.

This webinar will:

  • Compare the prevailing analog-to-data converter (ADC) architectures in terms
    of speed, resolution, area, and power consumption trade-offs
  • Describe the benefits of the successive-approximation register (SAR)-based
    ADC architecture for the medium and high speed ADCs
  • Describe how implementations of the SAR ADC architecture can reduce power
    consumption and area usage for 28-nm process technologies
  • Present the 28-nm DesignWare┬« Analog ADCs, which use the SAR-based
    architecture, and explain how they achieve 3x lower power consumption and 6x
    smaller area compared to previous generations

Who should attend: SoC Design Engineers, Managers and System

Azeredo-Leme, Senior Staff Engineer, DesignWare Analog IP,

Carlos Azeredo-Leme is a senior staff engineer for the
DesignWare Analog IP at Synopsys since 2009. Prior to joining Synopsys, he was
co-founder and member of the Board of Directors of Chipidea Microelectronics in
1993, where he held the position of Chief Technical Officer. There, he was
responsible for complete mixed-signal solutions, analog front-ends and RF. He
worked in the areas of audio, power management, cellular and wireless
communications and RF transceivers. Since 1994 he holds a position as Professor
at the Technical University of Lisbon (UTL-IST) in Portugal. His research
interests are in analog and mixed-signal design, focusing on low-power and
low-voltage. Carlos holds an MSEE from Technical University of Lisbon (UTL-IST)
in Portugal and a Ph.D. from ETH-Zurich in Switzerland.