See how design teams are saving weeks during implementation and signoff. Learn how PrimeTime Next-Generation ECO guidance and IC Compiler automatically fix DRC, setup and hold violations to reduce iterations and shorten ECO fixing turn around time.

This 30-minute webinar will focus on three ECO fixing topics to help you speed timing closure:

  • Technical overview of the new PrimeTime Next-Generation Guidance feature including its architecture and capabilities for single-machine ECO fixing
  • Results from these new capabilities at leading companies including STMicroelectronics, LSI, Cisco and Broadcom
  • Recommended flow for fast, automatic DRC, setup and hold fixing using PrimeTime and IC Compiler

This 30 minute webinar will be followed by a Q&A session with our Corporate Applications and R&D teams. 

Who should attend
Designers & managers responsible for ASIC and SoC design, implementation and signoff – especially those who are responsible for timing closure flows.

Troy Epperly
Staff Engineer, CAE
Implementation Group, Synopsys, Inc.

Troy Epperly is a Staff Corporate Applications Engineer focusing on PrimeTime performance and advanced technologies. After three years as an IC design engineer, he moved into EDA where he has spent the last ten years serving as an applications consultant and CAE responsible for physical design, logic synthesis and static timing analysis. Troy received his MSEE degree from Southern Methodist University and his BSEE degree from Lamar University.

Tzong-Maw Tsai
Director, CAE
Implementation Group, Synopsys, Inc.

Tzong-Maw Tsai is the CAE Director for timing signoff products and customer engagement support at Synopsys. Tzong-Maw and his team are responsible for supporting PrimeTime performance, signal integrity, delay calculation and ECO flows. He has been with Synopsys since 1992 and was responsible for logic synthesis and physical implementation products prior to his current role. Tzong-Maw received his BSEE degree from the University of Rochester.