Overview:
Learn how others are using PrimeTime Advanced OCV to speed design closure by eliminating overly pessimistic violations, and hear about TSMC’s views and support model for these new technologies. 

In our 2010 Webinar, Reducing Design Margins Using PrimeTime Advanced OCV, we showed that flat-derate On-Chip-Variation (OCV) for timing signoff is no longer practical for advanced designs at smaller geometries. 

This year’s webinar will focus on three Advanced OCV topics:

  • TSMC’s discussion of variation-aware analysis, the role of advanced modeling at 40nm and below, and their support model for these new technologies. 
  • New PrimeTime AOCV features including use of separate clock & data derate tables, OCV/AOCV precedence rules and new table generation techniques. 
  • Lessons learned from PrimeTime users – when to deploy AOCV, cost of adoption, use guidelines and expected results.

This 30 minute webinar will be followed by a Q&A session with our Corporate Applications and R&D teams. 

Who should attend 
Designers & managers responsible for reducing margins required for successful signoff 

Speakers:
Willy Chen , Program Manager , Design Methodology and Service Marketing, Design Infrastructure Marketing Division, TSMC

Willy Chen manages the Design Methodology and Service Marketing Program at TSMC, and is responsible for EDA eco-system partner management. He’s been with TSMC since 2000 and has overlooked the award winning Reference Flow and Active Accuracy Assurance (AAA) initiatives for EDA tool qualification of the company’s Open Innovation Platform(OIP). He has 16 years of experience in the semiconductor industry. Willy has a Masters Degree in Electrical and Computer Engineering from the University of California, Santa Barbara. 

Norb Heindl, Principal Corporate Applications Engineer, Implementation Group, Synopsys
Norb Heindl is currently a Principal Corporate Applications Engineer for STA at Synopsys supporting PrimeTime and NanoTime. After moving from design into EDA in 1994, he has focused on transistor and gate level static timing analysis while working as an Application Consultant and Corporate Applications Engineer. Norb received a BS in Electrical and Computer Engineering from University of Wisconsin.