In this webinar you will learn how new advances in clock gating and voltage threshold (Vt) optimization available in Design Compiler can reduce your dynamic and leakage power by 10-30%. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.

Speakers: 
Mary Ann White, Product Marketing Director, Synopsys 

Rishi Chawla, Sr. Application Engineering Manager, Synopsys