Reduce Power Consumption 30% with Advanced Synthesis Techniques
In this webinar you will learn how new advances in clock gating and voltage threshold (Vt) optimization available in Design Compiler can reduce your dynamic and leakage power by 10-30%. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.
Mary Ann White, Product Marketing Director, Synopsys
Rishi Chawla, Sr. Application Engineering Manager, Synopsys
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