Overview:
Synopsys Design Planning R&D will highlight the latest hierarchical design exploration and planning technology available in IC Compiler for handling today’s large 32/28nm designs.

Moderator:
Mark Bollar, Director of Product Marketing, IC Compiler, Synopsys
Mark Bollar is Director of Product Marketing focusing on design planning and CTS technology in IC Compiler. Mark has been involved in the wireless communication, semiconductor, and EDA industries for over 20 years, holding senior-level positions in both engineering and product marketing. Mark has a B.S.E.E degree, and received his M.S. in Engineering Management from the University of Southern California.

Presenter:
Thomas Andersen, Director of R&D, IC Compiler, Synopsys


Thomas Andersen is Director of R&D responsible for design planning, low power, chip finishing and overall hierarchical flow in IC Compiler. He is particularly focused on next generation high capacity design implementation. Thomas has held senior level positions in research and engineering at EDA and semi-conductor companies for over 12 years, originally starting his career at IBM Research. Thomas holds a MSc in EE from the University of Stuttgart, Germany and a PhD in EE from the University of Kaiserslautern, Germany.