Dealing with change has become more important than
ever—whether you need to support a new emerging standard or respond to new
functionality that your competition just released. And, designers also need to
deal with growing performance and power efficiency demands while meeting
time-to-market pressure.

So what about trading fixed hardware
implementations for a programmable hardware accelerator? Is it possible to
design such a programmable hardware that is flexible enough to deal with
multiple standards and different use cases, while meeting power, performance and
area constraints?

In this session, you will learn how custom processors
or ASIP (Application Specific Instruction-set Processors) can provide the right
trade-off between flexibility and power, performance and area requirements. You
will also learn how Synopsys Processor Designer greatly eases the implementation
and verification of a custom processor by enabling the creation of the optimized
RTL code, software tools such as assembler, linker, compiler and instruction-set
simulator as well as a SystemC model from a single formal input specification.

What you will learn:

  • Motivation for creation and development of custom processors
  • Custom processor requirements and development challenges
  • How Synopsys Processor Designer can meet the requirements and overcome the
    challenges of custom processor development
  • Demonstration of implementing a custom processor to replace fixed hardware

Who should attend:

  • Hardware engineers who are working on complex blocks that need to support
    multiple standards and/or modes
  • Hardware engineers who are working on complex control logic
  • Architects who want to make their design more scalable or evaluate a
    hardware accelerator in a system context
  • Processor designers who want to perform architectural analysis quickly with
    performance, power and area taken into account while not worrying about creating
    software tools manually

Taussig, Corporate Applications Engineer, Synopsys

Drew Taussig is a
Corporate Applications Engineer in the Systems Group at Synopsys, supporting
Processor Designer. Drew came to Synopsys from CoWare as part of the Processor
Designer Product Team. Prior to CoWare, Drew led the ASIC Systems Architecture
Team at Philips Semiconductors (now NXP). Drew has a Masters Degree in
Electrical Engineering from Stanford University and a BS in Electrical
Engineering and Computer Science from the University of Colorado at Boulder.