Power optimizing tips for Xilinx Virtex-5 FPGA designs
With the ever increasing power consumption trend in today's high-performance systems, managing the power within the system design budget is moving its priority up next to meeting the performance spec of the system design. With the adoption of FPGAs in more multiple markets and systems every year, driven by increasing performance/density and need to reduce overall system BOM cost, FPGA power consumption within the entire system is becoming a critical part of overall system budget.
This webcast will go through the factors contributing to power consumption in an FPGA design. It will explain how power is closely tied to the thermal consideration and reliability of the system. Finally, it will provide tips on how to optimize design for power consumption through changes in the FPGA environment and leveraging the FPGA features and tool options.
Attendees will Learn:
Who Should Attend:
FPGA designers, system architects, and PCB designers
Principal Engineer – Product and Market Development Group
Matt's principle concentration has been in the area of power consumption, especially with Virtex-4, Virtex-5, and all of Xilinx's future products. Matt has worked at Xilinx for 4 years and has worked with FPGAs for > 20 years having done close to 50 FPGA designs and worked on the system architecture of several large products. During this time Matt was the System Architect and Hardware Technical Lead at both Hewlett Packard (15 years) and Pinnacle Systems (5 years) with products ranging from Digital Synthesizers to Digital Radio Bit Error Rate Testers and most recently to Video Servers. Matt has patents in both Digital Radio and Video Systems and Xilinx FPGA patents. Matt has a B.S.E.E from Case Western Reserve University and an M.S.E.E. from Santa Clara University.
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