The massive growth in system integration places on-chip communication and interconnect at the center of system performance. Today architects are using virtual prototyping to predict system performance earlier in the design cycle, enabling new SoC designs to meet their performance objectives while avoiding the risk and cost of over-design.

Synopsys Platform Architect is a graphical environment for capturing, configuring, simulating and analyzing the system-level performance of next generation SoC architectures. Its efficient turnaround time, powerful analysis views, and available models make Platform Architect the premier choice for system-level performance analysis and optimization of ARM CoreLink interconnect for AMBA®-based SoCs.

CoreLink NIC-400 Network Interconnect from ARM is a fully configurable, hierarchical, low latency, low power interconnect IP that can be optimized to suit the requirements of a complex SoC using the AMBA protocols. The QoS-400 Advanced Quality of Service option featured in this webinar provides dynamic bandwidth or latency controlled regulators for the efficient and intelligent management of traffic in complex multi-master designs.

Hosted jointly by ARM and Synopsys, this webinar walks through a case study demonstration of system-level performance analysis and optimization featuring Synopsys Platform Architect, the Synopsys SBL-400 SystemC Bus Library for the ARM CoreLink NIC-400 Network Interconnect and ARM AMBA Designer configuration tool.

Who should attend:

System Designers, Product Architects, SoC Architects, and Project Managers

What Attendees will learn:
A mobile device SoC sub-system case study example will be used to illustrate how architects can:

  • See how to assemble a performance model of the mobile device SoC sub-system, including configuring the initial parameters of the SBL-400 interconnect using the Platform Architect flow with AMBA Designer
  • See how Platform Architect uses trace-driven application workloads to simulate and analyze multiple SBL-400 architecture configurations, including important QoS features of the interconnect and memory subsystem and how they impact system performance
  • See how information is easily shared with spreadsheet tools for sensitivity analysis to achieve the best architecture for performance, power, and cost