PCI Express 4.0 & Controller Design: Veni, Vidi, Vici
With the announced doubling of PCI Express’ maximum data rate to 16GT/s in PCIe 4.0, most of the attention has focused on the issues around SerDes design. After an overview of the new PCI Express 4.0 specification, this webinar will cover the most critical digital design challenges: link equalization, PHY interface design, dealing with multiple packets per clock cycle, and handling the higher bandwidth.
Attendees Will Learn About:
- How the specification recommends handling re-drivers and retimers
- Design changes to consider to handle new specifications on link equalization and the PHY interface
- How multiple packets per clock cycle will affect designs using PCIe 4.0
- Questions to ask for effective implementation of 16GT/s
Register for this webinar to learn about the key changes in the PCIe 4.0 specification and strategies for dealing with digital design challenges, including link equalization, PHY interface design, dealing with multiple packets per clock cycle, and handling the higher bandwidth.
Who should attend:
System and IC designers and architects, particularly those interested in moving from previous generations of PCI Express.
Technical Marketing Manager, Synopsys, Inc.
Richard Solomon is the Technical Marketing Manager for Synopsys’ DesignWare PCI Express Controller IP. He has been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec. Prior to joining Synopsys, Richard architected and led the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. He has served on the PCI-SIG Board of Directors for over 10 years, and is currently Vice-President of the PCI-SIG. Richard holds a BSEE from Rice University and 25 US Patents, many of which relate to PCI technology.
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