PCI Express 3.0: Learn how to perform PHY verification to the latest CEM and Base Specifications
PCI Express (™) is quickly moving to the 3rd generation of higher speed and performance with PCI Express 3.0 at 8GT/s. This is a significant upgrade which presents signal integrity challenges on the physical layer for engineers performing debug and validation to the latest CEM and Base Specifications issued by the PCI-SIG. This presentation will bring you up to speed on the PCI-SIG’s latest updates to the PCI Express 3.0 CEM and Base Specs, as well as testing guidance to ensure that engineers can accomplish a successful integration of PCI Express 3.0 into their designs. The presentation will also unveil a new toolset designed by Tektronix to simplify PHY Layer debug and verification of PCI Express 3.0 designs.
Attendees will learn:
- How to plan for electrical testing of new PCI Express Gen 3 Specification
- How to make proper instrument setup and measurements for PCI-SIG CEM and Base Specs
- The “why” behind new transmitter jitter measurements for PCI Express Gen 3
- Proper Receiver characterization techniques for PCI Express Gen 3
Sarah is the PCI Express Product Marketing Manager at Tektronix, Inc. Sarah represents Tektronix on the PCI-SIG. She holds a BSCS and MBA from the University of Portland and has been actively involved with computer and semiconductor technology development at Tektronix for over 5 years.
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