Slashing Iterations in Custom Design: a Parasitic-Aware Approach
Traditionally custom design has saved parasitic extraction for late in the flow. This made sense when most parasitics made only minor contributions to circuit performance. But as the relative importance of parasitics has grown with decreasing geometries, designing first and extracting later has become a prescription for infinite iteration. What you thought you designed is not what you get. In this Webinar based on actual Cadence tools, you will see how the latest custom design environments blend parasitic estimation into the design, implementation, and verification stages of the flow, and how having this data early in the flow can prevent—or at least minimize—design iterations due to unanticipated parasitic effects on circuit performance. The skills you build in this introductory Webinar will serve as the basis for several future sessions.
Who should attend:
IC custom designers doing either digital cell design or analog design and working at advanced geometries should not miss this event. IC physical design teams who work with advanced libraries should also attend to understand what is going on in their new libraries and how their own work can interact with the libraries’ assumptions.
Attendees will learn:
- A review of the key steps in a modern custom design flow.
- The importance of early parasitic estimation, and how these estimates can be integrated into the early stages of the flow.
- A familiarity with the methodology and specific tools in Cadence’s parasitic-aware custom flow
John Stabenow, Technical Marketing Group Director
John manages the Virtuoso Platform marketing team, including the Environment and Physical Design Product, as well as enabling technology. John rejoined Cadence in April of 2009, and has worked in EDA for more than 10 years at both Cadence and Synopsys. Prior to EDA, John worked at a variety of semiconductor companies in Silicon Valley
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