To meet high-performance computing (HPC) targets, specific challenges must be considered. Because the margins for achieving design closure on HPC designs at signoff are very small, every step of the physical implementation flow needs to address PPA metrics and avoid pessimism. HPC designs also need effective data-path skewing, from “place_opt” to “route_opt”, to meet their challenging frequency targets.

In this webinar attendees will learn about:

  • How the detail-route–centric architecture of Siemens’ Aprisa physical design solution makes it possible to derive the push-and-pull offsets during “place_opt” and effectively realize them in “route_opt”
  • How Aprisa’s comprised patented technologies correlate with the STA and DRC Signoff tools, allowing designers to adopt the flow very quickly for their advanced node designs
  • A case study for HPC implemented through Aprisa at an advanced process node, as well as how the above technologies help achieve the desired frequency target