Mobile communications, multimedia and consumer
SoCs must achieve the highest performance while consuming the minimal amount of
energy to achieve longer battery life and fit into lower cost packaging. Logic
libraries with a wide variety of voltage thresholds (VTs) and gate channel
lengths provide an efficient method for managing energy consumption. Synopsys’
multi-channel logic libraries and Power Optimization Kits take advantage of
low-power EDA tool flows and enable SoC designers to achieve timing closure
within the constraints of an aggressive power budget.

webinar will focus on:

  • How combining innovative power management techniques using multiple
    VTs/channel lengths in different SoC logic blocks delivers the optimal tradeoff
    in SoC watts per gigahertz
  • Ways to maximize system performance and minimize cost while slashing power
    budgets of SoC blocks operating at different clock speeds 

Length: 50 minutes + 10 minutes of Q&A

Who should attend: SoC design engineers, system
architects, project managers

Brock, Product Marketing Manager for Logic Libraries, Synopsys

Brock is Product Marketing Manager for Logic Libraries at Synopsys and brings 25
years of experience in the field. Prior to Synopsys, Ken held marketing
positions at Virage Logic, Simucad, Virtual Silicon, Compass Design Systems and
Mentor Graphics. Ken holds a Bachelor’s Degree in Electrical Engineering and an
MBA from Fairleigh Dickinson University.