The design of high-end embedded applications is
becoming increasingly difficult with the constant demand for higher performance.
At the same time, the power budget in many of these applications is fixed or
declining, increasing the design challenge. As a result, designers are forced to
make tradeoffs and deliver products that fall short of their goals. To address
these challenges, Synopsys has developed the DesignWare® ARC® HS Family of
embedded processors, which deliver more than 4200 DMIPS (per core) at less than
80 mW, giving designers the performance they need without compromising their
power budget.

This webinar will:

  • Discuss the capabilities and high-end embedded features offered with the ARC
    HS family.
  • Show how the processor cores can be quickly optimized for each instance on a
    SoC to maximize performance and minimize power consumption.
  • Describe the system-level benefits and show how designers can easily
    customize the processors to increase their products differentiation and value.

Length: 50 minutes + 10 minutes of Q&A

Who should attend: Design engineers, software
engineers, managers and system architects developing SoCs for applications such
as solid-state drives, connected appliances, automotive controllers, media
players, digital TV, set-top boxes and home networking

Thompson, Sr. Product Marketing Manager, ARC Processors

Thompson is responsible for the definition and marketing of the ARC
microprocessor products at Synopsys. Mike has more than 30 years of experience
in both the design and support of microprocessors, microcontrollers, IP cores,
and the development of embedded applications and tools. He has worked previously
for Actel, MIPS, ZiLOG, Philips/Signetics, and AMD. He has a BSEE from Northern
Illinois University and an MBA from Santa Clara University.