DSP cores occupy a key role in System-on-Chips (SoCs) targeting a wide range of end products, from smartphones and wearable devices, to wireless infrastructure. Depending on the application, these core implementations may target high or low speeds but they always seek to optimize area and power dissipation. In this webinar, CEVA and Synopsys will present results and best practices in hardening DSP cores to achieve performance targets while consuming low power and using minimal area in target applications, using DesignWare® Logic Libraries and Memory Compilers on a 28-nm process, along with Synopsys’ implementation and signoff tools. CEVA will also show how choosing the correct IP and methodology helps achieve optimal results and overcome physical design bottlenecks.

Attendees Will Learn:

  • How optimized embedded memories and logic libraries can enable your DSP design to deliver required performance while keeping area and power consumption low
  • How to select the correct design flow methodology to avoid physical design bottlenecks
  • How to work your way out of design bottlenecks when your find out you’re in one

Ken Brock
Product Marketing Manager, Logic Libraries, Synopsys

Ken Brock is Product Marketing Manager for Logic Libraries at Synopsys and brings 25 years of experience in the field. Prior to Synopsys, Ken held marketing positions at Virage Logic, Simucad, Virtual Silicon, Compass Design Systems and Mentor Graphics. Ken holds a Bachelor’s Degree in Electrical Engineering and an MBA from Fairleigh Dickinson University.

Ran Snir
VLSI Director, CEVA

Ran Snir serves as a VLSI Director in CEVA since 2011. In his role, he is responsible for all VLSI aspects related to CEVA’s DSP products. Prior to this, Mr. Snir was the VLSI department manager, design team and verification team manager at CEVA. Mr. Snir has worked for CEVA in its DSP Group since 1999, and has held several development and managerial R&D positions. Mr. Snir holds a BSc degree in electronics engineering from Tel-Aviv University.