Optimize Your FPGA System for Cost, Power, and Flexibility Using Partial Reconfiguration
Partial Reconfiguration is the ability to dynamically modify blocks of FPGA logic by downloading partial bit files while the remaining logic on the device continues to operate without interruption. Xilinx Partial Reconfiguration technology allows designers to change functionality on the fly, eliminating the need to fully reconfigure and re-establish links, dramatically enhancing the flexibility that FPGAs offer. Radio, video or bus links or other vital functions can remain established while other functions are reloaded on demand.
By leveraging Partial Reconfiguration with the ISE Design Suite, FPGA designers have a powerful solution to:
- Reduce FPGA size or count (and therefore cost) by time-sharing functionality
- Reduce dynamic power consumption by loading functions on-demand
- Increase solution flexibility by time-multiplexing design functionality
In this Webcast, attendees will learn:
- Details on the design flow for Partial Reconfiguration Technology
- How real users are benefiting from Partial Reconfiguration
- Design considerations to maximize the benefits
David Dye, Software Product Marketing Engineer, Xilinx
David Dye joined Xilinx in 1994. As a Software Product Marketing Manager at Xilinx, Dye is responsible for driving Partial Reconfiguration tool requirements and strategies for Xilinx software and silicon.
Dye brings more than 15 years of design, applications and marketing experience to Xilinx. He has served in a variety of technical roles in the marketing and support organizations during his tenure.
Dye holds a bachelor of science in Electrical Engineering degree from Carnegie Mellon University.
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