A breakthrough in lane reduction and overall interface simplification between FPGA and high speed digital converters
In multichannel, high resolution applications such as wireless multimode base stations, medical scanning devices and military multiband and multimode radios, the interface between the FPGA and the analog-to-digital or digital-to-analog converter can become extremely complex due to the very high number of digital lanes. NXP has developed high speed data converters based on the JESD204A high speed gigabit digital serial interface that significantly reduces the number of lanes, thus simplifying the overall interface to the digital baseband processing.

During this training, you’ll learn about the JESD204A serial interface, NXP’s CGV implementation of the JESD204A interface, and its inherent performance and implementation benefits.

Key Learning Points:

  • Jedec JESD204A interface
  • Comparison of high speed serial interfaces
  • JESD204A implementation at ADC and DAC level
  • Key benefits of JESD204A implementation
  • NXP's CGV implementation of JESD204A
  • Interoperability with the major FPGA suppliers
  • Existing JESD204A based portfolio and design-in support tools


Jarek Lucek, Business Development Manger, NXP
Jarek Lucek is currently a Business Development Manager for high speed data converters in the Americas at NXP. He has over 10 years experience in the development and application support of RF/analog systems and products in the wireless market. He also has over 5 years experience in business development of RF/analog products and solutions in the semiconductor industry.

Brad Loisel, Application Engineer, NXP
Brad Loisel is an Application Engineer for NXP supporting high speed data converter products in the Americas. He has over 15 years experience in RF/analog mixed signal product development in the consumer and defense electronics industries, and he has over 6 years experience in the semiconductor industry.