Next Generation BERT Ensures Signal Integrity in High-speed Digital Designs
R&D and test engineers need to characterize the next generation of mobile, computer and networking devices. Designs require higher bandwidth, less space and less power, but time pressure is increasing. Will Moore’s law continue?
Today’s connected-life and small high-end consumer devices require an ever-increasing level of integration and device complexity. Enabling unprecedented functionality in high-speed digital devices introduces several new challenges:
- Time pressure due to time consuming tests and adoption of the next generation of test standards
- Higher data rates in combination with non-ideal transmit materials (e.g. FR4) and tighter performance margins while keeping signal integrity under control (example: How to count a BER with a closed eye at the input of the analyzer?)
- Testing highly integrated designs with limited access to individual test points
This webcast talks about today’s and upcoming challenges, explains different solution approaches including Agilent’s newest innovation in the BERT market.
Who Should Attend:
This webcast is recommended for the following audience:
- R&D engineers, lead engineers and managers responsible for next-generation computer, consumer or communication devices
- R&D engineers, lead engineers and mangers interested in trends and new test approaches/concepts in high-speed digital device verification, reducing testing time and optimizing the performance margins of high-speed digital devices
- R&D engineers who characterize and verify compliance of chips, devices, boards and systems with serial I/O ports up to 16 Gb/s and 32 Gb/s
- Engineers involved with serial bus standards such as: PCI Express®, USB, MIPI, STA/SAS, DisplayPort, SD UHS-II, Fibre Channel, QPI, HyperTransport, memory buses, backplanes, repeaters, active optical cables, Thunderbolt, 10 GbE, 100 GbE (optical and electrical), SFP+, CFP2/4 transceivers, CEI
Juergen Beck, General Manager and VP Agilent Technologies, Digital & Photonic Test Division
Juergen Beck is Vice President & General Manager of Agilent’s Digital & Photonic Test Division, which includes photonic test and measurement instruments, pulse and arbitrary waveform generators (AWG) and bit error ratio testers (BERT) for photonic and high speed digital test applications.
Prior to his current responsibilities, Juergen held multiple management positions in R&D, Manufacturing and Operations and as General Manager across various businesses within Hewlett Packard and Agilent Technologies.
Juergen joined Hewlett-Packard in 1984 as an R&D engineer after graduating from the University of Stuttgart with a master degree in mechanical engineering.
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