New PCI Express 3.0 Testing Approaches for PHY and Protocol Layers
Tektronix recently announced new capability for testing the latest PCI Express 3.0 Revision. This new high speed serial standard presents many challenges to chip and system designers. The new revision effectively doubles the data rate while transmitting over the same PCB properties (FR-4); leading to careful management of signal integrity issues for today’s designer. Learn how to manage through these and other PCI Express-related challenges with help from Tektronix experts on this webinar.
Attendees will learn:
- New PCI Express 3 test solutions to address challenges from physical to protocol layer for characterization and compliance
- New measurement requirements for transmitter and receiver equalization, channel de-embedding, and jitter measurements like deterministic Pulse Width Jitter (PWJ) and Uncorrelated Jitter
- How to quickly and easily trace protocol interactions from the transaction layer down to the physical layer and debug elusive transaction, link training and power management problems
Randy White, Serial Data Technical Marketing Manager, Tektronix
Randy White is the serial applications technical marketing manager at Tektronix. Randy has worked with various aspects of test and measurement solutions at Tektronix over the past few years. He has given seminars on high-speed serial measurements and is actively involved in many working groups for high-speed serial standards. He holds a BSEE from Oregon State University in Corvallis
Please disable any pop-up blockers for proper viewing of this webinar.