The use of BGA probes for probing DDR DRAM is becoming more popular as design gets more complex and compact and data rate gets higher. DDR3 and DDR4 data rate is increasing from 800MT/s to possibly 3200MT/s. Memory system designers now have huge concerns on probing meeting the high bandwidth requirement for best signal fidelity and also are in need of analysis tool to ease making measurements. This webcast describes a new probe correction method used to extend the bandwidth of the DDR BGA probe to provide more margins in testing signal integrity and minimize error introduced by the BGA probe. It also includes analysis tools available today to help make measurement to reduce test cost and time.

Who should view this webcast:
This webcast will be valuable to engineers who are currently working on DDR memory design and would be migrating to higher speed DDR memory in near future.

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Ai-Lee Kuan, Memory Product Manager, Digital Test Division
Ai-Lee Kuan joined Agilent Malaysia in 2001 and held various positions in test equipment manufacturing as test and product engineer. In 2004, Ai-Lee joined the marketing team as the Asia regional application engineer. Her expertise is in high speed bus application which include DDR memory physical layer and protocol application. 

Ai-Lee is now working with the DTD oscilloscopes marketing team with area of focus in memory physical layer characterization and compliance test. 

Ai-Lee holds a Bachelor’s degree in electrical and electronics from University of Science Malaysia.