Learn how the advanced features in NanoTime enable designers to accurately and quickly identify timing issues early in the design cycle to avoid expensive silicon re-spins. The new SI-Noise analysis and CCS noise model generation features allow users to accurately analyze the noise impact on timing and to generate noise models for full-chip analysis.

Chirag PateStaff Engineer, CAE, Implementation Group, Synopsys Inc

Chirag Patel joined Synopsys in June of 2006 as a member of the NanoTime CAE team. He has a Bachelor of Engineering (Electronics) degree from the National Institute of Technology (Surat, India) and an MSEE from Purdue University. Besides his 4+ years of experience in Applications Engineering, Chirag also has seven years of IC design experience, including time spent as a member of the technical staff at Sun Microsystems. Chirag has a deep understanding of NanoTime transistor-level STA as well as gate-level full-chip timing analysis with PrimeTime.

Peter O’Brien, Senior Staff R&D Engineer, Implementation Group, Synopsys, Inc.

Peter O’Brien is a Senior Staff R&D Engineer on the NanoTime development team at Synopsys. Peter started his EDA software development career at Digital Equipment Corporation in 1985 where he worked on the analysis of timing and signal integrity issues for the design of high-end VAX systems. In 2002, he joined Synopsys as part of the PathMill/NanoTime development team and today works on timing analysis, noise analysis, and parasitic reduction. Peter has 11 publications and 5 patents in the areas of delay modeling, timing analysis, parasitic reduction, and circuit optimization. Peter received BS degrees in Mathematics and Electrical Engineering and an MS degree in Electrical Engineering from the Massachusetts Institute of Technology.