Increasing multi-channel receive and transmit densities on monolithic integrated circuits (ICs) have enabled exciting new architectural analyses with regards to the design of phased arrays, radars, electronic warfare, and satellite communication systems. However, this increased density requires that systems designers analyze the architectural trade-offs in terms of power consumption, complexity, dynamic range performance and overall system cost.

This webinar addresses, using measured results, how the use of hardened digital signal processing (DSP) blocks residing on digitizer ICs, instead of those similar blocks residing in an FPGA, result in dramatic system-level improvements.

Attendees will learn about:

  • Which now possess much DSP capability to simplify otherwise complex multi-channel systems
  • Using hardened DSP on digitizer ICs, which is more power efficient than FPGA DSP
  • How hardened DSP can correct both digital and RF front-end anomalies
  • The use of sample rate decimation/interpolation/numerically-controlled oscillators and hardened programmable finite impulse response filters leads to wideband subarray calibrations.