For years the industry has wanted to synthesize high-level code, such as SystemC, directly into a form usable in an RTL design flow. Until recently, that has been a dream except for a few specific types of blocks such as datapaths. But recent breakthroughs in synthesis algorithms and growing understanding of how to use SystemC to express a wider variety of structures are dissolving that limitation. In this Webinar we will describe and illustrate how to create SystemC code for synthesis, and how to analyze your high-level design, drive the new SystemC-to-RTL synthesis tools, and take the measures that will ensure the kind of netlist you want down-stream. It’s not just for datapaths any more. 
Who should attend: Architects, logic designers, RTL synthesis users, design managers 
Mark Warren, Group Director of System Level Design group, Cadence 

Mark Warren is Group Director of the System Level Design group in Cadence. His current role is to manage the field organization and drive the development of the Cadence C-to-Silicon Compiler. Prior to joining Cadence, Mark was an ASIC designer at GE Aerospace/Lockheed Martin and spent 12 years as a key contributor on the VCS simulator at Synopsys/Viewlogic. Mark holds a B.Tech in Electrical Engineering from the Rochester Institute of Technology and has participated in graduate studies at Syracuse University and Santa Clara University.